HAL2 Migrator
LL HRTIM APIs listing for migration ¶
This section provides a full listing of the HAL1 APIs for migration. It includes the various constants, enumerations, structures, functions, and macros.
LL HRTIM constants ¶
|
HAL1 |
series |
HAL2 |
|---|---|---|
|
LL_HRTIM_ADCTRIG_1 |
g4, h7 |
LL_HRTIM_ADCTRIG1 |
|
LL_HRTIM_ADCTRIG_10 |
g4 |
LL_HRTIM_ADCTRIG10 |
|
LL_HRTIM_ADCTRIG_2 |
g4, h7 |
LL_HRTIM_ADCTRIG2 |
|
LL_HRTIM_ADCTRIG_3 |
g4, h7 |
LL_HRTIM_ADCTRIG3 |
|
LL_HRTIM_ADCTRIG_4 |
g4, h7 |
LL_HRTIM_ADCTRIG4 |
|
LL_HRTIM_ADCTRIG_5 |
g4 |
LL_HRTIM_ADCTRIG5 |
|
LL_HRTIM_ADCTRIG_6 |
g4 |
LL_HRTIM_ADCTRIG6 |
|
LL_HRTIM_ADCTRIG_7 |
g4 |
LL_HRTIM_ADCTRIG7 |
|
LL_HRTIM_ADCTRIG_8 |
g4 |
LL_HRTIM_ADCTRIG8 |
|
LL_HRTIM_ADCTRIG_9 |
g4 |
LL_HRTIM_ADCTRIG9 |
|
LL_HRTIM_ADCTRIG_UPDATE_TIMER_A |
g4, h7 |
LL_HRTIM_ADCTRIG_UPDATE_TIMA |
|
LL_HRTIM_ADCTRIG_UPDATE_TIMER_B |
g4, h7 |
LL_HRTIM_ADCTRIG_UPDATE_TIMB |
|
LL_HRTIM_ADCTRIG_UPDATE_TIMER_C |
g4, h7 |
LL_HRTIM_ADCTRIG_UPDATE_TIMC |
|
LL_HRTIM_ADCTRIG_UPDATE_TIMER_D |
g4, h7 |
LL_HRTIM_ADCTRIG_UPDATE_TIMD |
|
LL_HRTIM_ADCTRIG_UPDATE_TIMER_E |
g4, h7 |
LL_HRTIM_ADCTRIG_UPDATE_TIME |
|
LL_HRTIM_ADCTRIG_UPDATE_TIMER_F |
g4, h7 |
LL_HRTIM_ADCTRIG_UPDATE_TIMF |
|
LL_HRTIM_BM_CLKSRC_TIMER_A |
g4, h7 |
LL_HRTIM_BM_CLKSRC_TIMA |
|
LL_HRTIM_BM_CLKSRC_TIMER_B |
g4, h7 |
LL_HRTIM_BM_CLKSRC_TIMB |
|
LL_HRTIM_BM_CLKSRC_TIMER_C |
g4, h7 |
LL_HRTIM_BM_CLKSRC_TIMC |
|
LL_HRTIM_BM_CLKSRC_TIMER_D |
g4, h7 |
LL_HRTIM_BM_CLKSRC_TIMD |
|
LL_HRTIM_BM_CLKSRC_TIMER_E |
g4, h7 |
LL_HRTIM_BM_CLKSRC_TIME |
|
LL_HRTIM_BM_CLKSRC_TIMER_F |
g4, h7 |
LL_HRTIM_BM_CLKSRC_TIMF |
|
LL_HRTIM_BM_CLKSRC_FHRTIM |
g4, h7 |
LL_HRTIM_BM_CLKSRC_HRTIM |
|
LL_HRTIM_BM_MODE_CONTINOUS |
g4, h7 |
LL_HRTIM_BM_MODE_CONTINUOUS |
|
LL_HRTIM_BM_MODE_SINGLESHOT |
g4, h7 |
LL_HRTIM_BM_MODE_SINGLE_SHOT |
|
LL_HRTIM_BM_TRIG_EVENT_ONCHIP |
g4, h7 |
LL_HRTIM_BM_TRIG_ONCHIP |
|
LL_HRTIM_BM_TRIG_TIMC_CMP2 |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_BM_TRIG_TIMD_CMP1 |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_BM_TRIG_TIME_RESET |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_CROSSBAR_EEV_1 |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_CROSSBAR_EEV_2 |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_CROSSBAR_EEV_3 |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_CROSSBAR_EEV_4 |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_CROSSBAR_EEV_5 |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_CROSSBAR_EEV_6 |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_CROSSBAR_EEV_7 |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_CROSSBAR_EEV_8 |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_CROSSBAR_EEV_9 |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_CROSSBAR_EEV_10 |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_DT_PRESCALER_DIV16 |
g4, h7 |
LL_HRTIM_DT_PRESCALER_MUL16 |
|
LL_HRTIM_EEFLTR_BLANKINGFLTR1 |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_EEFLTR_BLANKINGFLTR2 |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_EEFLTR_BLANKINGFLTR3 |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_EEFLTR_BLANKINGFLTR4 |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_EEFLTR_BLANKINGFLTR5 |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_EEFLTR_BLANKINGFLTR6 |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_EEFLTR_BLANKINGFLTR7 |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_EEFLTR_BLANKINGFLTR8 |
g4, h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_MODE_RETRIGGERABLE |
g4, h7 |
LL_HRTIM_MODE_SINGLESHOT_RETRIGGERABLE |
|
LL_HRTIM_ADCTRIG_SRC13_MCMP1 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_MASTER_CMP1 |
|
LL_HRTIM_ADCTRIG_SRC13_MCMP2 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_MASTER_CMP2 |
|
LL_HRTIM_ADCTRIG_SRC13_MCMP3 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_MASTER_CMP3 |
|
LL_HRTIM_ADCTRIG_SRC13_MCMP4 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_MASTER_CMP4 |
|
LL_HRTIM_ADCTRIG_SRC13_MPER |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_MASTER_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC13_TIMACMP2 |
h7 |
LL_HRTIM_ADCTRIG_SRC13_TIMA_CMP2 |
|
LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_TIMA_CMP3 |
|
LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_TIMA_CMP4 |
|
LL_HRTIM_ADCTRIG_SRC13_TIMAPER |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_TIMA_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC13_TIMARST |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_TIMA_RESET |
|
LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2 |
h7 |
LL_HRTIM_ADCTRIG_SRC13_TIMB_CMP2 |
|
LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_TIMB_CMP3 |
|
LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_TIMB_CMP4 |
|
LL_HRTIM_ADCTRIG_SRC13_TIMBPER |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_TIMB_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC13_TIMBRST |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_TIMB_RESET |
|
LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2 |
h7 |
LL_HRTIM_ADCTRIG_SRC13_TIMC_CMP2 |
|
LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_TIMC_CMP3 |
|
LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_TIMC_CMP4 |
|
LL_HRTIM_ADCTRIG_SRC13_TIMCPER |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_TIMC_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2 |
h7 |
LL_HRTIM_ADCTRIG_SRC13_TIMD_CMP2 |
|
LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_TIMD_CMP3 |
|
LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_TIMD_CMP4 |
|
LL_HRTIM_ADCTRIG_SRC13_TIMDPER |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_TIMD_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC13_TIMECMP2 |
h7 |
LL_HRTIM_ADCTRIG_SRC13_TIME_CMP2 |
|
LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_TIME_CMP3 |
|
LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_TIME_CMP4 |
|
LL_HRTIM_ADCTRIG_SRC13_TIMEPER |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC13_TIME_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2 |
g4 |
LL_HRTIM_ADCTRIG_SRC13_TIMF_CMP2 |
|
LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3 |
g4 |
LL_HRTIM_ADCTRIG_SRC13_TIMF_CMP3 |
|
LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4 |
g4 |
LL_HRTIM_ADCTRIG_SRC13_TIMF_CMP4 |
|
LL_HRTIM_ADCTRIG_SRC13_TIMFPER |
g4 |
LL_HRTIM_ADCTRIG_SRC13_TIMF_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC13_TIMFRST |
g4 |
LL_HRTIM_ADCTRIG_SRC13_TIMF_RESET |
|
LL_HRTIM_ADCTRIG_SRC24_MCMP1 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_MASTER_CMP1 |
|
LL_HRTIM_ADCTRIG_SRC24_MCMP2 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_MASTER_CMP2 |
|
LL_HRTIM_ADCTRIG_SRC24_MCMP3 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_MASTER_CMP3 |
|
LL_HRTIM_ADCTRIG_SRC24_MCMP4 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_MASTER_CMP4 |
|
LL_HRTIM_ADCTRIG_SRC24_MPER |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_MASTER_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_TIMA_CMP2 |
|
LL_HRTIM_ADCTRIG_SRC24_TIMACMP3 |
h7 |
LL_HRTIM_ADCTRIG_SRC24_TIMA_CMP3 |
|
LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_TIMA_CMP4 |
|
LL_HRTIM_ADCTRIG_SRC24_TIMAPER |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_TIMA_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_TIMB_CMP2 |
|
LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3 |
h7 |
LL_HRTIM_ADCTRIG_SRC24_TIMB_CMP3 |
|
LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_TIMB_CMP4 |
|
LL_HRTIM_ADCTRIG_SRC24_TIMBPER |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_TIMB_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_TIMC_CMP2 |
|
LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3 |
h7 |
LL_HRTIM_ADCTRIG_SRC24_TIMC_CMP3 |
|
LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_TIMC_CMP4 |
|
LL_HRTIM_ADCTRIG_SRC24_TIMCPER |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_TIMC_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC24_TIMCRST |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_TIMC_RESET |
|
LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_TIMD_CMP2 |
|
LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3 |
h7 |
LL_HRTIM_ADCTRIG_SRC24_TIMD_CMP3 |
|
LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_TIMD_CMP4 |
|
LL_HRTIM_ADCTRIG_SRC24_TIMDPER |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_TIMD_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC24_TIMDRST |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_TIMD_RESET |
|
LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_TIME_CMP2 |
|
LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_TIME_CMP3 |
|
LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_TIME_CMP4 |
|
LL_HRTIM_ADCTRIG_SRC24_TIMERST |
g4, h7 |
LL_HRTIM_ADCTRIG_SRC24_TIME_RESET |
|
LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2 |
g4 |
LL_HRTIM_ADCTRIG_SRC24_TIMF_CMP2 |
|
LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3 |
g4 |
LL_HRTIM_ADCTRIG_SRC24_TIMF_CMP3 |
|
LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4 |
g4 |
LL_HRTIM_ADCTRIG_SRC24_TIMF_CMP4 |
|
LL_HRTIM_ADCTRIG_SRC24_TIMFPER |
g4 |
LL_HRTIM_ADCTRIG_SRC24_TIMF_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC579_MCMP1 |
g4 |
LL_HRTIM_ADCTRIG_SRC579_MASTER_CMP1 |
|
LL_HRTIM_ADCTRIG_SRC579_MCMP2 |
g4 |
LL_HRTIM_ADCTRIG_SRC579_MASTER_CMP2 |
|
LL_HRTIM_ADCTRIG_SRC579_MCMP3 |
g4 |
LL_HRTIM_ADCTRIG_SRC579_MASTER_CMP3 |
|
LL_HRTIM_ADCTRIG_SRC579_MCMP4 |
g4 |
LL_HRTIM_ADCTRIG_SRC579_MASTER_CMP4 |
|
LL_HRTIM_ADCTRIG_SRC579_MPER |
g4 |
LL_HRTIM_ADCTRIG_SRC579_MASTER_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC579_TIMA_PER |
g4 |
LL_HRTIM_ADCTRIG_SRC579_TIMA_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC579_TIMA_RST |
g4 |
LL_HRTIM_ADCTRIG_SRC579_TIMA_RESET |
|
LL_HRTIM_ADCTRIG_SRC579_TIMB_PER |
g4 |
LL_HRTIM_ADCTRIG_SRC579_TIMB_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC579_TIMB_RST |
g4 |
LL_HRTIM_ADCTRIG_SRC579_TIMB_RESET |
|
LL_HRTIM_ADCTRIG_SRC579_TIMC_PER |
g4 |
LL_HRTIM_ADCTRIG_SRC579_TIMC_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC579_TIMD_PER |
g4 |
LL_HRTIM_ADCTRIG_SRC579_TIMD_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC579_TIME_PER |
g4 |
LL_HRTIM_ADCTRIG_SRC579_TIME_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC579_TIMF_PER |
g4 |
LL_HRTIM_ADCTRIG_SRC579_TIMF_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC579_TIMF_RST |
g4 |
LL_HRTIM_ADCTRIG_SRC579_TIMF_RESET |
|
LL_HRTIM_ADCTRIG_SRC6810_MCMP1 |
g4 |
LL_HRTIM_ADCTRIG_SRC6810_MASTER_CMP1 |
|
LL_HRTIM_ADCTRIG_SRC6810_MCMP2 |
g4 |
LL_HRTIM_ADCTRIG_SRC6810_MASTER_CMP2 |
|
LL_HRTIM_ADCTRIG_SRC6810_MCMP3 |
g4 |
LL_HRTIM_ADCTRIG_SRC6810_MASTER_CMP3 |
|
LL_HRTIM_ADCTRIG_SRC6810_MCMP4 |
g4 |
LL_HRTIM_ADCTRIG_SRC6810_MASTER_CMP4 |
|
LL_HRTIM_ADCTRIG_SRC6810_MPER |
g4 |
LL_HRTIM_ADCTRIG_SRC6810_MASTER_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER |
g4 |
LL_HRTIM_ADCTRIG_SRC6810_TIMA_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER |
g4 |
LL_HRTIM_ADCTRIG_SRC6810_TIMB_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER |
g4 |
LL_HRTIM_ADCTRIG_SRC6810_TIMC_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST |
g4 |
LL_HRTIM_ADCTRIG_SRC6810_TIMC_RESET |
|
LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER |
g4 |
LL_HRTIM_ADCTRIG_SRC6810_TIMD_PERIOD |
|
LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST |
g4 |
LL_HRTIM_ADCTRIG_SRC6810_TIMD_RESET |
|
LL_HRTIM_ADCTRIG_SRC6810_TIME_RST |
g4 |
LL_HRTIM_ADCTRIG_SRC6810_TIME_RESET |
|
LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER |
g4 |
LL_HRTIM_ADCTRIG_SRC6810_TIMF_PERIOD |
|
LL_HRTIM_BM_TRIG_EVENT_7 |
g4, h7 |
LL_HRTIM_BM_TRIG_EEVG |
|
LL_HRTIM_BM_TRIG_EVENT_8 |
g4, h7 |
LL_HRTIM_BM_TRIG_EEVH |
|
LL_HRTIM_BM_TRIG_TIMA_EVENT7 |
g4, h7 |
LL_HRTIM_BM_TRIG_TIMA_EEVG |
|
LL_HRTIM_BM_TRIG_TIMD_EVENT8 |
g4, h7 |
LL_HRTIM_BM_TRIG_TIMA_EEVH |
|
LL_HRTIM_BURSTDMA_CR2 |
g4 |
LL_HRTIM_BURSTDMA_TIMCR2 |
|
LL_HRTIM_BURSTDMA_EEFR3 |
g4 |
LL_HRTIM_BURSTDMA_TIMEEFR3 |
|
LL_HRTIM_BURSTDMA_TIMMCR |
g4, h7 |
LL_HRTIM_BURSTDMA_TIMCR |
|
LL_HRTIM_CAPTURETRIG_EEV_1 |
g4, h7 |
LL_HRTIM_CAPTURETRIG_EEV_1 |
|
LL_HRTIM_CAPTURETRIG_EEV_10 |
g4, h7 |
LL_HRTIM_CAPTURETRIG_EEV_10 |
|
LL_HRTIM_CAPTURETRIG_EEV_2 |
g4, h7 |
LL_HRTIM_CAPTURETRIG_EEV_2 |
|
LL_HRTIM_CAPTURETRIG_EEV_3 |
g4, h7 |
LL_HRTIM_CAPTURETRIG_EEV_3 |
|
LL_HRTIM_CAPTURETRIG_EEV_4 |
g4, h7 |
LL_HRTIM_CAPTURETRIG_EEV_4 |
|
LL_HRTIM_CAPTURETRIG_EEV_5 |
g4, h7 |
LL_HRTIM_CAPTURETRIG_EEV_5 |
|
LL_HRTIM_CAPTURETRIG_EEV_6 |
g4, h7 |
LL_HRTIM_CAPTURETRIG_EEV_6 |
|
LL_HRTIM_CAPTURETRIG_EEV_7 |
g4, h7 |
LL_HRTIM_CAPTURETRIG_EEV_7 |
|
LL_HRTIM_CAPTURETRIG_EEV_8 |
g4, h7 |
LL_HRTIM_CAPTURETRIG_EEV_8 |
|
LL_HRTIM_CAPTURETRIG_EEV_9 |
g4, h7 |
LL_HRTIM_CAPTURETRIG_EEV_9 |
|
LL_HRTIM_CAPTURETRIG_TA1_RESET |
g4, h7 |
LL_HRTIM_CAPTURETRIG_TA1_RESET |
|
LL_HRTIM_CAPTURETRIG_TA1_SET |
g4, h7 |
LL_HRTIM_CAPTURETRIG_TA1_SET |
|
LL_HRTIM_CAPTURETRIG_TB1_RESET |
g4, h7 |
LL_HRTIM_CAPTURETRIG_TB1_RESET |
|
LL_HRTIM_CAPTURETRIG_TB1_SET |
g4, h7 |
LL_HRTIM_CAPTURETRIG_TB1_SET |
|
LL_HRTIM_CAPTURETRIG_TC1_RESET |
g4, h7 |
LL_HRTIM_CAPTURETRIG_TC1_RESET |
|
LL_HRTIM_CAPTURETRIG_TC1_SET |
g4, h7 |
LL_HRTIM_CAPTURETRIG_TC1_SET |
|
LL_HRTIM_CAPTURETRIG_TD1_RESET |
g4, h7 |
LL_HRTIM_CAPTURETRIG_TD1_RESET |
|
LL_HRTIM_CAPTURETRIG_TD1_SET |
g4, h7 |
LL_HRTIM_CAPTURETRIG_TD1_SET |
|
LL_HRTIM_CAPTURETRIG_TE1_RESET |
g4, h7 |
LL_HRTIM_CAPTURETRIG_TE1_RESET |
|
LL_HRTIM_CAPTURETRIG_TE1_SET |
g4, h7 |
LL_HRTIM_CAPTURETRIG_TIMA_CHE1_SET |
|
LL_HRTIM_CAPTURETRIG_TF1_RESET |
g4 |
LL_HRTIM_CAPTURETRIG_TIMA_CHE1_RESET |
|
LL_HRTIM_CAPTURETRIG_TF1_SET |
g4 |
LL_HRTIM_CAPTURETRIG_TIMA_CHF1_SET |
|
LL_HRTIM_CAPTURETRIG_TIMA_CMP1 |
g4, h7 |
LL_HRTIM_CAPTURETRIG_TIMA_CMP1 |
|
LL_HRTIM_CAPTURETRIG_TIMA_CMP2 |
g4, h7 |
LL_HRTIM_CAPTURETRIG_TIMA_CMP2 |
|
LL_HRTIM_CAPTURETRIG_TIMB_CMP1 |
g4, h7 |
LL_HRTIM_CAPTURETRIG_TIMB_CMP1 |
|
LL_HRTIM_CAPTURETRIG_TIMB_CMP2 |
g4, h7 |
LL_HRTIM_CAPTURETRIG_TIMB_CMP2 |
|
LL_HRTIM_CAPTURETRIG_TIMC_CMP1 |
g4, h7 |
LL_HRTIM_CAPTURETRIG_TIMC_CMP1 |
|
LL_HRTIM_CAPTURETRIG_TIMC_CMP2 |
g4, h7 |
LL_HRTIM_CAPTURETRIG_TIMC_CMP2 |
|
LL_HRTIM_CAPTURETRIG_TIMD_CMP1 |
g4, h7 |
LL_HRTIM_CAPTURETRIG_TIMD_CMP1 |
|
LL_HRTIM_CAPTURETRIG_TIMD_CMP2 |
g4, h7 |
LL_HRTIM_CAPTURETRIG_TIMD_CMP2 |
|
LL_HRTIM_CAPTURETRIG_TIME_CMP1 |
g4, h7 |
LL_HRTIM_CAPTURETRIG_TIME_CMP1 |
|
LL_HRTIM_CAPTURETRIG_TIME_CMP2 |
g4, h7 |
LL_HRTIM_CAPTURETRIG_TIME_CMP2 |
|
LL_HRTIM_CAPTURETRIG_TIMF_CMP1 |
g4 |
|
|
LL_HRTIM_CAPTURETRIG_TIMF_CMP2 |
g4 |
|
|
LL_HRTIM_CAPTUREUNIT_1 |
g4, h7 |
LL_HRTIM_CAPTURE_UNIT_1 |
|
LL_HRTIM_CAPTUREUNIT_2 |
g4, h7 |
LL_HRTIM_CAPTURE_UNIT_2 |
|
LL_HRTIM_COMPAREUNIT_2 |
g4, h7 |
LL_HRTIM_COMPARE_UNIT_2 |
|
LL_HRTIM_COMPAREUNIT_4 |
g4, h7 |
LL_HRTIM_COMPARE_UNIT_4 |
|
LL_HRTIM_CPPSTAT_OUTPUT1 |
g4, h7 |
LL_HRTIM_CPPSTAT_OUT1 |
|
LL_HRTIM_CPPSTAT_OUTPUT2 |
g4, h7 |
LL_HRTIM_CPPSTAT_OUT2 |
|
LL_HRTIM_CROSSBAR_MASTERCMP1 |
h7 |
LL_HRTIM_OUTPUTSET_MASTER_CMP1 |
|
LL_HRTIM_CROSSBAR_MASTERCMP2 |
h7 |
LL_HRTIM_OUTPUTSET_MASTER_CMP2 |
|
LL_HRTIM_CROSSBAR_MASTERCMP3 |
h7 |
LL_HRTIM_OUTPUTSET_MASTER_CMP3 |
|
LL_HRTIM_CROSSBAR_MASTERCMP4 |
h7 |
LL_HRTIM_OUTPUTSET_MASTER_CMP4 |
|
LL_HRTIM_CROSSBAR_MASTERPER |
h7 |
LL_HRTIM_OUTPUTSET_MASTER_PERIOD |
|
LL_HRTIM_CROSSBAR_NONE |
h7 |
LL_HRTIM_OUTPUTSET_NONE |
|
LL_HRTIM_CROSSBAR_RESYNC |
h7 |
LL_HRTIM_OUTPUTSET_RESYNC |
|
LL_HRTIM_CROSSBAR_TIMCMP1 |
h7 |
LL_HRTIM_OUTPUTSET_CMP1 |
|
LL_HRTIM_CROSSBAR_TIMCMP2 |
h7 |
LL_HRTIM_OUTPUTSET_CMP2 |
|
LL_HRTIM_CROSSBAR_TIMCMP3 |
h7 |
LL_HRTIM_OUTPUTSET_CMP3 |
|
LL_HRTIM_CROSSBAR_TIMCMP4 |
h7 |
LL_HRTIM_OUTPUTSET_CMP4 |
|
LL_HRTIM_CROSSBAR_TIMEV_1 |
h7 |
LL_HRTIM_CROSSBAR_TIMEV_1 |
|
LL_HRTIM_CROSSBAR_TIMEV_2 |
h7 |
LL_HRTIM_CROSSBAR_TIMEV_2 |
|
LL_HRTIM_CROSSBAR_TIMEV_3 |
h7 |
LL_HRTIM_CROSSBAR_TIMEV_3 |
|
LL_HRTIM_CROSSBAR_TIMEV_4 |
h7 |
LL_HRTIM_CROSSBAR_TIMEV_4 |
|
LL_HRTIM_CROSSBAR_TIMEV_5 |
h7 |
LL_HRTIM_CROSSBAR_TIMEV_5 |
|
LL_HRTIM_CROSSBAR_TIMEV_6 |
h7 |
LL_HRTIM_CROSSBAR_TIMEV_6 |
|
LL_HRTIM_CROSSBAR_TIMEV_7 |
h7 |
LL_HRTIM_CROSSBAR_TIMEV_7 |
|
LL_HRTIM_CROSSBAR_TIMEV_8 |
h7 |
LL_HRTIM_CROSSBAR_TIMEV_8 |
|
LL_HRTIM_CROSSBAR_TIMEV_9 |
h7 |
LL_HRTIM_CROSSBAR_TIMEV_9 |
|
LL_HRTIM_CROSSBAR_TIMPER |
h7 |
LL_HRTIM_OUTPUTSET_PERIOD |
|
LL_HRTIM_CROSSBAR_UPDATE |
h7 |
LL_HRTIM_OUTPUTSET_UPDATE |
|
LL_HRTIM_DACTRIG_DACTRIGOUT_1 |
g4, h7 |
LL_HRTIM_DACTRIG_DACTRIGOUT1 |
|
LL_HRTIM_DACTRIG_DACTRIGOUT_2 |
g4, h7 |
LL_HRTIM_DACTRIG_DACTRIGOUT2 |
|
LL_HRTIM_DACTRIG_DACTRIGOUT_3 |
g4, h7 |
LL_HRTIM_DACTRIG_DACTRIGOUT3 |
|
LL_HRTIM_DCDR_COUNTER |
g4 |
LL_HRTIM_DCDR_RESET |
|
LL_HRTIM_DCDR_OUT1SET |
g4 |
LL_HRTIM_DCDR_OUT1_SET |
|
LL_HRTIM_DCDS_OUT1RST |
g4 |
LL_HRTIM_DCDS_OUT1_RESET |
|
LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS |
g4 |
REMOVED (Use set bit api to HRTIM_DLLCR_CALEN bit directly) |
|
LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT |
g4 |
REMOVED (Use reset bit api to HRTIM_DLLCR_CALEN bit directly) |
|
LL_HRTIM_EEFLTR_BLANKINGCMP1 |
g4, h7 |
LL_HRTIM_BLK_RST_CMP1 |
|
LL_HRTIM_EEFLTR_BLANKINGCMP2 |
g4, h7 |
LL_HRTIM_BLK_RST_CMP2 |
|
LL_HRTIM_EEFLTR_BLANKINGCMP3 |
g4, h7 |
LL_HRTIM_BLK_RST_CMP3 |
|
LL_HRTIM_EEFLTR_BLANKINGCMP4 |
g4, h7 |
LL_HRTIM_BLK_RST_CMP4 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1 |
g4 |
LL_HRTIM_BLK_TIMA_TBRST_TBCMP1 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4 |
g4 |
LL_HRTIM_BLK_TIMA_TBRST_TBCMP4 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2 |
g4 |
LL_HRTIM_BLK_TIMA_CHB2 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1 |
g4 |
LL_HRTIM_BLK_TIMA_TCRST_TCCMP1 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4 |
g4 |
LL_HRTIM_BLK_TIMA_TCRST_TCCMP4 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1 |
g4 |
LL_HRTIM_BLK_TIMA_TFRST_TFCMP1 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1 |
g4 |
LL_HRTIM_BLK_TIMA_TDRST_TDCMP1 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2 |
g4 |
LL_HRTIM_BLK_TIMA_TERST_TECMP2 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1 |
g4 |
LL_HRTIM_BLK_TIMB_TARST_TACMP1 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4 |
g4 |
LL_HRTIM_BLK_TIMB_TARST_TACMP4 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2 |
g4 |
LL_HRTIM_BLK_TIMB_CHA2 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1 |
g4 |
LL_HRTIM_BLK_TIMB_TCRST_TCCMP1 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2 |
g4 |
LL_HRTIM_BLK_TIMB_TCRST_TCCMP2 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2 |
g4 |
LL_HRTIM_BLK_TIMB_TFRST_TFCMP2 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2 |
g4 |
LL_HRTIM_BLK_TIMB_TDRST_TDCMP2 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1 |
g4 |
LL_HRTIM_BLK_TIMB_TERST_TECMP1 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2 |
g4 |
LL_HRTIM_BLK_TIMC_TARST_TACMP2 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1 |
g4 |
LL_HRTIM_BLK_TIMC_TBRST_TBCMP1 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4 |
g4 |
LL_HRTIM_BLK_TIMC_TBRST_TBCMP4 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1 |
g4 |
LL_HRTIM_BLK_TIMC_TFRST_TFCMP1 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1 |
g4 |
LL_HRTIM_BLK_TIMC_TDRST_TDCMP1 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4 |
g4 |
LL_HRTIM_BLK_TIMC_TDRST_TDCMP4 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2 |
g4 |
LL_HRTIM_BLK_TIMC_CHD2 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4 |
g4 |
LL_HRTIM_BLK_TIMC_TERST_TECMP4 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1 |
g4 |
LL_HRTIM_BLK_TIMD_TARST_TACMP1 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2 |
g4 |
LL_HRTIM_BLK_TIMD_TBRST_TBCMP2 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1 |
g4 |
LL_HRTIM_BLK_TIMD_TCRST_TCCMP1 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2 |
g4 |
LL_HRTIM_BLK_TIMD_TCRST_TCCMP2 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2 |
g4 |
LL_HRTIM_BLK_TIMD_CHC2 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1 |
g4 |
LL_HRTIM_BLK_TIMD_TERST_TECMP1 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4 |
g4 |
LL_HRTIM_BLK_TIMD_TERST_TECMP4 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4 |
g4 |
LL_HRTIM_BLK_TIMD_TFRST_TFCMP4 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2 |
g4 |
LL_HRTIM_BLK_TIME_TARST_TACMP2 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1 |
g4 |
LL_HRTIM_BLK_TIME_TBRST_TBCMP1 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1 |
g4 |
LL_HRTIM_BLK_TIME_TCRST_TCCMP1 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4 |
g4 |
LL_HRTIM_BLK_TIME_TFRST_TFCMP4 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2 |
g4 |
LL_HRTIM_BLK_TIME_CHF2 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1 |
g4 |
LL_HRTIM_BLK_TIME_TDRST_TDCMP1 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4 |
g4 |
LL_HRTIM_BLK_TIME_TDRST_TDCMP4 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2 |
g4 |
LL_HRTIM_BLK_TIME_CHD2 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4 |
g4 |
LL_HRTIM_BLK_TIMF_TARST_TACMP4 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2 |
g4 |
LL_HRTIM_BLK_TIMF_TBRST_TBCMP2 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4 |
g4 |
LL_HRTIM_BLK_TIMF_TCRST_TCCMP4 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2 |
g4 |
LL_HRTIM_BLK_TIMF_TDRST_TDCMP2 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4 |
g4 |
LL_HRTIM_BLK_TIMF_TDRST_TDCMP4 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1 |
g4 |
LL_HRTIM_BLK_TIMF_TERST_TECMP1 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4 |
g4 |
LL_HRTIM_BLK_TIMF_TERST_TECMP4 |
|
LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2 |
g4 |
LL_HRTIM_BLK_TIMF_CHE2 |
|
LL_HRTIM_EEFLTR_NONE |
g4, h7 |
LL_HRTIM_EEFLTR_NONE |
|
LL_HRTIM_EEFLTR_WINDOWINGCMP2 |
g4, h7 |
LL_HRTIM_EEFLTR_WIN_RST_CMP2 |
|
LL_HRTIM_EEFLTR_WINDOWINGCMP3 |
g4, h7 |
LL_HRTIM_EEFLTR_WIN_RST_CMP3 |
|
LL_HRTIM_EEFLTR_WINDOWINGTIM |
g4, h7 |
LL_HRTIM_EEFLTR_WIN_TIMWIN |
|
LL_HRTIM_EEV10SRC_ADC5_AWD1 |
g4 |
REMOVED (No ADC5 in the supported series) |
|
LL_HRTIM_EEV10SRC_COMP7_OUT |
g4 |
LL_HRTIM_EEV10SRC_COMP7 |
|
LL_HRTIM_EEV1SRC_COMP2_OUT |
g4 |
LL_HRTIM_EEV1SRC_COMP2_OUT |
|
LL_HRTIM_EEV2SRC_COMP4_OUT |
g4 |
LL_HRTIM_EEV2SRC_COMP4 |
|
LL_HRTIM_EEV3SRC_COMP6_OUT |
g4 |
LL_HRTIM_EEV3SRC_COMP6 |
|
LL_HRTIM_EEV4SRC_COMP1_OUT |
g4 |
LL_HRTIM_EEV4SRC_COMP1 |
|
LL_HRTIM_EEV4SRC_COMP5_OUT |
g4 |
LL_HRTIM_EEV4SRC_COMP5 |
|
LL_HRTIM_EEV5SRC_COMP3_OUT |
g4 |
LL_HRTIM_EEV5SRC_COMP3 |
|
LL_HRTIM_EEV5SRC_COMP7_OUT |
g4 |
LL_HRTIM_EEV5SRC_COMP7 |
|
LL_HRTIM_EEV6SRC_COMP1_OUT |
g4 |
LL_HRTIM_EEV6SRC_COMP1 |
|
LL_HRTIM_EEV6SRC_COMP2_OUT |
g4 |
LL_HRTIM_EEV6SRC_COMP2 |
|
LL_HRTIM_EEV7SRC_COMP4_OUT |
g4 |
LL_HRTIM_EEV7SRC_COMP4 |
|
LL_HRTIM_EEV8SRC_ADC4_AWD1 |
g4 |
LL_HRTIM_EEV8SRC_ADC4 |
|
LL_HRTIM_EEV8SRC_COMP3_OUT |
g4 |
LL_HRTIM_EEV8SRC_COMP3 |
|
LL_HRTIM_EEV8SRC_COMP6_OUT |
g4 |
LL_HRTIM_EEV8SRC_COMP6 |
|
LL_HRTIM_EEV9SRC_COMP4_OUT |
g4 |
LL_HRTIM_EEV9SRC_COMP4 |
|
LL_HRTIM_EEV9SRC_COMP5_OUT |
g4 |
LL_HRTIM_EEV9SRC_COMP5 |
|
LL_HRTIM_EE_SENSITIVITY_BOTHEDGES |
g4, h7 |
LL_HRTIM_EE_SENSITIVITY_RISING_FALLING |
|
LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE |
g4, h7 |
LL_HRTIM_EE_SENSITIVITY_FALLING |
|
LL_HRTIM_EE_SENSITIVITY_RISINGEDGE |
g4, h7 |
LL_HRTIM_EE_SENSITIVITY_RISING |
|
LL_HRTIM_EE_SRC_1 |
h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_EE_SRC_2 |
h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_EE_SRC_3 |
h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_EE_SRC_4 |
h7 |
Not implemented yet in HAL2. |
|
LL_HRTIM_EVENT_1 |
g4, h7 |
LL_HRTIM_EEV1 |
|
LL_HRTIM_EVENT_10 |
g4, h7 |
LL_HRTIM_EEV10 |
|
LL_HRTIM_EVENT_2 |
g4, h7 |
LL_HRTIM_EEV2 |
|
LL_HRTIM_EVENT_3 |
g4, h7 |
LL_HRTIM_EEV3 |
|
LL_HRTIM_EVENT_4 |
g4, h7 |
LL_HRTIM_EEV4 |
|
LL_HRTIM_EVENT_5 |
g4, h7 |
LL_HRTIM_EEV5 |
|
LL_HRTIM_EVENT_6 |
g4, h7 |
LL_HRTIM_EEV6 |
|
LL_HRTIM_EVENT_7 |
g4, h7 |
LL_HRTIM_EEV7 |
|
LL_HRTIM_EVENT_8 |
g4, h7 |
LL_HRTIM_EEV8 |
|
LL_HRTIM_EVENT_9 |
g4, h7 |
LL_HRTIM_EEV9 |
|
LL_HRTIM_FAULT_1 |
g4, h7 |
LL_HRTIM_FLT1 |
|
LL_HRTIM_FAULT_2 |
g4, h7 |
LL_HRTIM_FLT2 |
|
LL_HRTIM_FAULT_3 |
g4, h7 |
LL_HRTIM_FLT3 |
|
LL_HRTIM_FAULT_4 |
g4, h7 |
LL_HRTIM_FLT4 |
|
LL_HRTIM_FAULT_5 |
g4, h7 |
LL_HRTIM_FLT5 |
|
LL_HRTIM_FAULT_6 |
g4 |
LL_HRTIM_FLT6 |
|
LL_HRTIM_FLT_BLANKING_MOVING |
g4 |
LL_HRTIM_FLT_BLK_MOVING |
|
LL_HRTIM_FLT_BLANKING_RSTALIGNED |
g4 |
LL_HRTIM_FLT_BLK_RSTALIGNED |
|
LL_HRTIM_FLT_SRC_DIGITALINPUT |
g4, h7 |
LL_HRTIM_FLT1SRC_GPIO |
|
LL_HRTIM_FLT_SRC_EEVINPUT |
g4 |
LL_HRTIM_FLT1SRC_EEV1 |
|
LL_HRTIM_FLT_SRC_INTERNAL |
g4, h7 |
LL_HRTIM_FLT1SRC_COMP2 |
|
LL_HRTIM_IPPSTAT_OUTPUT1 |
g4, h7 |
LL_HRTIM_IPPSTAT_OUT1 |
|
LL_HRTIM_IPPSTAT_OUTPUT2 |
g4, h7 |
LL_HRTIM_IPPSTAT_OUT2 |
|
LL_HRTIM_OUTPUTRESET_EEV_1 |
g4 |
Not implemented yet in HAL2. |
|
LL_HRTIM_OUTPUTRESET_EEV_10 |
g4 |
Not implemented yet in HAL2. |
|
LL_HRTIM_OUTPUTRESET_EEV_2 |
g4 |
Not implemented yet in HAL2. |
|
LL_HRTIM_OUTPUTRESET_EEV_3 |
g4 |
Not implemented yet in HAL2. |
|
LL_HRTIM_OUTPUTRESET_EEV_4 |
g4 |
Not implemented yet in HAL2. |
|
LL_HRTIM_OUTPUTRESET_EEV_5 |
g4 |
Not implemented yet in HAL2. |
|
LL_HRTIM_OUTPUTRESET_EEV_6 |
g4 |
Not implemented yet in HAL2. |
|
LL_HRTIM_OUTPUTRESET_EEV_7 |
g4 |
Not implemented yet in HAL2. |
|
LL_HRTIM_OUTPUTRESET_EEV_8 |
g4 |
Not implemented yet in HAL2. |
|
LL_HRTIM_OUTPUTRESET_EEV_9 |
g4 |
Not implemented yet in HAL2. |
|
LL_HRTIM_OUTPUTRESET_MASTERCMP1 |
g4 |
LL_HRTIM_OUTPUTRESET_MASTER_CMP1 |
|
LL_HRTIM_OUTPUTRESET_MASTERCMP2 |
g4 |
LL_HRTIM_OUTPUTRESET_MASTER_CMP2 |
|
LL_HRTIM_OUTPUTRESET_MASTERCMP3 |
g4 |
LL_HRTIM_OUTPUTRESET_MASTER_CMP3 |
|
LL_HRTIM_OUTPUTRESET_MASTERCMP4 |
g4 |
LL_HRTIM_OUTPUTRESET_MASTER_CMP4 |
|
LL_HRTIM_OUTPUTRESET_MASTERPER |
g4 |
LL_HRTIM_OUTPUTRESET_MASTER_PERIOD |
|
LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMA_TBCMP1 |
|
LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMA_TBCMP2 |
|
LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMA_TCCMP2 |
|
LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMA_TCCMP3 |
|
LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMA_TDCMP1 |
|
LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMA_TDCMP2 |
|
LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMA_TECMP3 |
|
LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMA_TECMP4 |
|
LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMA_TFCMP4 |
|
LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMB_TBCMP1 |
|
LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMB_TBCMP2 |
|
LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMB_TCCMP2 |
|
LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMB_TCCMP3 |
|
LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMB_TDCMP1 |
|
LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMB_TDCMP2 |
|
LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMB_TECMP3 |
|
LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMB_TECMP4 |
|
LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMB_TFCMP4 |
|
LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMC_TBCMP1 |
|
LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMC_TBCMP2 |
|
LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMC_TCCMP2 |
|
LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMC_TCCMP3 |
|
LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMC_TDCMP1 |
|
LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMC_TDCMP2 |
|
LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMC_TECMP3 |
|
LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMC_TECMP4 |
|
LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMC_TFCMP2 |
|
LL_HRTIM_OUTPUTRESET_TIMCMP1 |
g4 |
LL_HRTIM_OUTPUTRESET_CMP1 |
|
LL_HRTIM_OUTPUTRESET_TIMCMP2 |
g4 |
LL_HRTIM_OUTPUTRESET_CMP2 |
|
LL_HRTIM_OUTPUTRESET_TIMCMP3 |
g4 |
LL_HRTIM_OUTPUTRESET_CMP3 |
|
LL_HRTIM_OUTPUTRESET_TIMCMP4 |
g4 |
LL_HRTIM_OUTPUTRESET_CMP4 |
|
LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMD_TACMP1 |
|
LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMD_TACMP4 |
|
LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMD_TBCMP2 |
|
LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMD_TBCMP4 |
|
LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMD_TCCMP4 |
|
LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMD_TECMP1 |
|
LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMD_TECMP4 |
|
LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMD_TFCMP1 |
|
LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMD_TFCMP3 |
|
LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 |
g4 |
LL_HRTIM_OUTPUTRESET_TIME_TACMP4 |
|
LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 |
g4 |
LL_HRTIM_OUTPUTRESET_TIME_TBCMP3 |
|
LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 |
g4 |
LL_HRTIM_OUTPUTRESET_TIME_TBCMP4 |
|
LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 |
g4 |
LL_HRTIM_OUTPUTRESET_TIME_TCCMP1 |
|
LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2 |
g4 |
LL_HRTIM_OUTPUTRESET_TIME_TCCMP2 |
|
LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 |
g4 |
LL_HRTIM_OUTPUTRESET_TIME_TDCMP1 |
|
LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 |
g4 |
LL_HRTIM_OUTPUTRESET_TIME_TDCMP2 |
|
LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 |
g4 |
LL_HRTIM_OUTPUTRESET_TIME_TFCMP3 |
|
LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 |
g4 |
LL_HRTIM_OUTPUTRESET_TIME_TFCMP4 |
|
LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMF_TACMP3 |
|
LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMF_TBCMP1 |
|
LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMF_TBCMP4 |
|
LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMF_TCCMP1 |
|
LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMF_TCCMP4 |
|
LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMF_TDCMP3 |
|
LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMF_TDCMP4 |
|
LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMF_TECMP2 |
|
LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 |
g4 |
LL_HRTIM_OUTPUTRESET_TIMF_TECMP3 |
|
LL_HRTIM_OUTPUTRESET_TIMPER |
g4 |
LL_HRTIM_OUTPUTRESET_PERIOD |
|
LL_HRTIM_OUTPUTSET_EEV_1 |
g4 |
LL_HRTIM_CROSSBAR_EEV_1 |
|
LL_HRTIM_OUTPUTSET_EEV_10 |
g4 |
LL_HRTIM_CROSSBAR_EEV_10 |
|
LL_HRTIM_OUTPUTSET_EEV_2 |
g4 |
LL_HRTIM_CROSSBAR_EEV_2 |
|
LL_HRTIM_OUTPUTSET_EEV_3 |
g4 |
LL_HRTIM_CROSSBAR_EEV_3 |
|
LL_HRTIM_OUTPUTSET_EEV_4 |
g4 |
LL_HRTIM_CROSSBAR_EEV_4 |
|
LL_HRTIM_OUTPUTSET_EEV_5 |
g4 |
LL_HRTIM_CROSSBAR_EEV_5 |
|
LL_HRTIM_OUTPUTSET_EEV_6 |
g4 |
LL_HRTIM_CROSSBAR_EEV_6 |
|
LL_HRTIM_OUTPUTSET_EEV_7 |
g4 |
LL_HRTIM_CROSSBAR_EEV_7 |
|
LL_HRTIM_OUTPUTSET_EEV_8 |
g4 |
LL_HRTIM_CROSSBAR_EEV_8 |
|
LL_HRTIM_OUTPUTSET_EEV_9 |
g4 |
LL_HRTIM_CROSSBAR_EEV_9 |
|
LL_HRTIM_OUTPUTSET_MASTERCMP1 |
g4 |
LL_HRTIM_OUTPUTSET_MASTER_CMP1 |
|
LL_HRTIM_OUTPUTSET_MASTERCMP2 |
g4 |
LL_HRTIM_OUTPUTSET_MASTER_CMP2 |
|
LL_HRTIM_OUTPUTSET_MASTERCMP3 |
g4 |
LL_HRTIM_OUTPUTSET_MASTER_CMP3 |
|
LL_HRTIM_OUTPUTSET_MASTERCMP4 |
g4 |
LL_HRTIM_OUTPUTSET_MASTER_CMP4 |
|
LL_HRTIM_OUTPUTSET_MASTERPER |
g4 |
LL_HRTIM_OUTPUTSET_MASTER_PERIOD |
|
LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 |
g4 |
LL_HRTIM_OUTPUTSET_TIMA_TBCMP1 |
|
LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 |
g4 |
LL_HRTIM_OUTPUTSET_TIMA_TBCMP2 |
|
LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 |
g4 |
LL_HRTIM_OUTPUTSET_TIMA_TCCMP2 |
|
LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 |
g4 |
LL_HRTIM_OUTPUTSET_TIMA_TCCMP3 |
|
LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 |
g4 |
LL_HRTIM_OUTPUTSET_TIMA_TDCMP1 |
|
LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 |
g4 |
LL_HRTIM_OUTPUTSET_TIMA_TDCMP2 |
|
LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 |
g4 |
LL_HRTIM_OUTPUTSET_TIMA_TECMP3 |
|
LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 |
g4 |
LL_HRTIM_OUTPUTSET_TIMA_TECMP4 |
|
LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 |
g4 |
LL_HRTIM_OUTPUTSET_TIMA_TFCMP4 |
|
LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 |
g4 |
LL_HRTIM_OUTPUTSET_TIMB_TACMP1 |
|
LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 |
g4 |
LL_HRTIM_OUTPUTSET_TIMB_TACMP2 |
|
LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 |
g4 |
LL_HRTIM_OUTPUTSET_TIMB_TCCMP3 |
|
LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 |
g4 |
LL_HRTIM_OUTPUTSET_TIMB_TCCMP4 |
|
LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 |
g4 |
LL_HRTIM_OUTPUTSET_TIMB_TDCMP3 |
|
LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 |
g4 |
LL_HRTIM_OUTPUTSET_TIMB_TDCMP4 |
|
LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 |
g4 |
LL_HRTIM_OUTPUTSET_TIMB_TECMP1 |
|
LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 |
g4 |
LL_HRTIM_OUTPUTSET_TIMB_TECMP2 |
|
LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 |
g4 |
LL_HRTIM_OUTPUTSET_TIMB_TFCMP3 |
|
LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 |
g4 |
LL_HRTIM_OUTPUTSET_TIMC_TACMP2 |
|
LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 |
g4 |
LL_HRTIM_OUTPUTSET_TIMC_TACMP3 |
|
LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 |
g4 |
LL_HRTIM_OUTPUTSET_TIMC_TBCMP2 |
|
LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 |
g4 |
LL_HRTIM_OUTPUTSET_TIMC_TBCMP3 |
|
LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 |
g4 |
LL_HRTIM_OUTPUTSET_TIMC_TDCMP2 |
|
LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 |
g4 |
LL_HRTIM_OUTPUTSET_TIMC_TDCMP4 |
|
LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 |
g4 |
LL_HRTIM_OUTPUTSET_TIMC_TECMP3 |
|
LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 |
g4 |
LL_HRTIM_OUTPUTSET_TIMC_TECMP4 |
|
LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 |
g4 |
LL_HRTIM_OUTPUTSET_TIMC_TFCMP2 |
|
LL_HRTIM_OUTPUTSET_TIMCMP1 |
g4 |
LL_HRTIM_OUTPUTSET_CMP1 |
|
LL_HRTIM_OUTPUTSET_TIMCMP2 |
g4 |
LL_HRTIM_OUTPUTSET_CMP2 |
|
LL_HRTIM_OUTPUTSET_TIMCMP3 |
g4 |
LL_HRTIM_OUTPUTSET_CMP3 |
|
LL_HRTIM_OUTPUTSET_TIMCMP4 |
g4 |
LL_HRTIM_OUTPUTSET_CMP4 |
|
LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 |
g4 |
LL_HRTIM_OUTPUTSET_TIMD_TACMP1 |
|
LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 |
g4 |
LL_HRTIM_OUTPUTSET_TIMD_TACMP4 |
|
LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 |
g4 |
LL_HRTIM_OUTPUTSET_TIMD_TBCMP2 |
|
LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 |
g4 |
LL_HRTIM_OUTPUTSET_TIMD_TBCMP4 |
|
LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 |
g4 |
LL_HRTIM_OUTPUTSET_TIMD_TCCMP4 |
|
LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 |
g4 |
LL_HRTIM_OUTPUTSET_TIMD_TECMP1 |
|
LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 |
g4 |
LL_HRTIM_OUTPUTSET_TIMD_TECMP4 |
|
LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 |
g4 |
LL_HRTIM_OUTPUTSET_TIMD_TFCMP1 |
|
LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 |
g4 |
LL_HRTIM_OUTPUTSET_TIMD_TFCMP3 |
|
LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 |
g4 |
LL_HRTIM_OUTPUTSET_TIME_TACMP4 |
|
LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 |
g4 |
LL_HRTIM_OUTPUTSET_TIME_TBCMP3 |
|
LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 |
g4 |
LL_HRTIM_OUTPUTSET_TIME_TBCMP4 |
|
LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 |
g4 |
LL_HRTIM_OUTPUTSET_TIME_TCCMP1 |
|
LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2 |
g4 |
LL_HRTIM_OUTPUTSET_TIME_TCCMP2 |
|
LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 |
g4 |
LL_HRTIM_OUTPUTSET_TIME_TDCMP1 |
|
LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 |
g4 |
LL_HRTIM_OUTPUTSET_TIME_TDCMP2 |
|
LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 |
g4 |
LL_HRTIM_OUTPUTSET_TIME_TFCMP3 |
|
LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 |
g4 |
LL_HRTIM_OUTPUTSET_TIME_TFCMP4 |
|
LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 |
g4 |
LL_HRTIM_OUTPUTSET_TIMF_TACMP3 |
|
LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 |
g4 |
LL_HRTIM_OUTPUTSET_TIMF_TBCMP1 |
|
LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 |
g4 |
LL_HRTIM_OUTPUTSET_TIMF_TBCMP4 |
|
LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 |
g4 |
LL_HRTIM_OUTPUTSET_TIMF_TCCMP1 |
|
LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 |
g4 |
LL_HRTIM_OUTPUTSET_TIMF_TCCMP4 |
|
LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 |
g4 |
LL_HRTIM_OUTPUTSET_TIMF_TDCMP3 |
|
LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 |
g4 |
LL_HRTIM_OUTPUTSET_TIMF_TDCMP4 |
|
LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 |
g4 |
LL_HRTIM_OUTPUTSET_TIMF_TECMP2 |
|
LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 |
g4 |
LL_HRTIM_OUTPUTSET_TIMF_TECMP3 |
|
LL_HRTIM_OUTPUTSET_TIMPER |
g4 |
LL_HRTIM_OUTPUTSET_PERIOD |
|
LL_HRTIM_OUTPUT_TA1 |
g4, h7 |
LL_HRTIM_OUTPUT_CHA1 |
|
LL_HRTIM_OUTPUT_TA2 |
g4, h7 |
LL_HRTIM_OUTPUT_CHA2 |
|
LL_HRTIM_OUTPUT_TB1 |
g4, h7 |
LL_HRTIM_OUTPUT_CHB1 |
|
LL_HRTIM_OUTPUT_TB2 |
g4, h7 |
LL_HRTIM_OUTPUT_CHB2 |
|
LL_HRTIM_OUTPUT_TC1 |
g4, h7 |
LL_HRTIM_OUTPUT_CHC1 |
|
LL_HRTIM_OUTPUT_TC2 |
g4, h7 |
LL_HRTIM_OUTPUT_CHC2 |
|
LL_HRTIM_OUTPUT_TD1 |
g4, h7 |
LL_HRTIM_OUTPUT_CHD1 |
|
LL_HRTIM_OUTPUT_TD2 |
g4, h7 |
LL_HRTIM_OUTPUT_CHD2 |
|
LL_HRTIM_OUTPUT_TE1 |
g4, h7 |
LL_HRTIM_OUTPUT_CHE1 |
|
LL_HRTIM_OUTPUT_TE2 |
g4, h7 |
LL_HRTIM_OUTPUT_CHE2 |
|
LL_HRTIM_OUTPUT_TF1 |
g4 |
LL_HRTIM_OUTPUT_CHF1 |
|
LL_HRTIM_OUTPUT_TF2 |
g4 |
LL_HRTIM_OUTPUT_CHF2 |
|
LL_HRTIM_OUT_FAULTSTATE_NO_ACTION |
g4, h7 |
LL_HRTIM_OUT_FAULTSTATE_NONE |
|
LL_HRTIM_RESETTRIG_EEV_1 |
g4, h7 |
LL_HRTIM_RESETTRIG_EEV1 |
|
LL_HRTIM_RESETTRIG_EEV_10 |
g4, h7 |
LL_HRTIM_RESETTRIG_EEV10 |
|
LL_HRTIM_RESETTRIG_EEV_2 |
g4, h7 |
LL_HRTIM_RESETTRIG_EEV2 |
|
LL_HRTIM_RESETTRIG_EEV_3 |
g4, h7 |
LL_HRTIM_RESETTRIG_EEV3 |
|
LL_HRTIM_RESETTRIG_EEV_4 |
g4, h7 |
LL_HRTIM_RESETTRIG_EEV4 |
|
LL_HRTIM_RESETTRIG_EEV_5 |
g4, h7 |
LL_HRTIM_RESETTRIG_EEV5 |
|
LL_HRTIM_RESETTRIG_EEV_6 |
g4, h7 |
LL_HRTIM_RESETTRIG_EEV6 |
|
LL_HRTIM_RESETTRIG_EEV_7 |
g4, h7 |
LL_HRTIM_RESETTRIG_EEV7 |
|
LL_HRTIM_RESETTRIG_EEV_8 |
g4, h7 |
LL_HRTIM_RESETTRIG_EEV8 |
|
LL_HRTIM_RESETTRIG_EEV_9 |
g4, h7 |
LL_HRTIM_RESETTRIG_EEV9 |
|
LL_HRTIM_RESETTRIG_MASTER_PER |
g4, h7 |
LL_HRTIM_RESETTRIG_MASTER_PERIOD |
|
LL_HRTIM_RESETTRIG_OTHER1_CMP1 |
g4, h7 |
LL_HRTIM_RESETTRIG_TIMA_TBCMP1 |
|
LL_HRTIM_RESETTRIG_OTHER1_CMP2 |
g4, h7 |
LL_HRTIM_RESETTRIG_TIMA_TBCMP2 |
|
LL_HRTIM_RESETTRIG_OTHER1_CMP4 |
g4, h7 |
LL_HRTIM_RESETTRIG_TIMA_TBCMP4 |
|
LL_HRTIM_RESETTRIG_OTHER2_CMP1 |
g4, h7 |
LL_HRTIM_RESETTRIG_TIMA_TCCMP1 |
|
LL_HRTIM_RESETTRIG_OTHER2_CMP2 |
g4, h7 |
LL_HRTIM_RESETTRIG_TIMA_TCCMP2 |
|
LL_HRTIM_RESETTRIG_OTHER2_CMP4 |
g4, h7 |
LL_HRTIM_RESETTRIG_TIMA_TCCMP4 |
|
LL_HRTIM_RESETTRIG_OTHER3_CMP1 |
g4, h7 |
LL_HRTIM_RESETTRIG_TIMA_TDCMP1 |
|
LL_HRTIM_RESETTRIG_OTHER3_CMP2 |
g4, h7 |
LL_HRTIM_RESETTRIG_TIMA_TDCMP2 |
|
LL_HRTIM_RESETTRIG_OTHER3_CMP4 |
g4, h7 |
LL_HRTIM_RESETTRIG_TIMA_TDCMP4 |
|
LL_HRTIM_RESETTRIG_OTHER4_CMP1 |
g4, h7 |
LL_HRTIM_RESETTRIG_TIMA_TECMP1 |
|
LL_HRTIM_RESETTRIG_OTHER4_CMP2 |
g4, h7 |
LL_HRTIM_RESETTRIG_TIMA_TECMP2 |
|
LL_HRTIM_RESETTRIG_OTHER4_CMP4 |
g4, h7 |
LL_HRTIM_RESETTRIG_TIMA_TECMP4 |
|
LL_HRTIM_RESETTRIG_OTHER5_CMP1 |
g4 |
LL_HRTIM_RESETTRIG_TIMA_TFCMP1 |
|
LL_HRTIM_RESETTRIG_OTHER5_CMP2 |
g4 |
LL_HRTIM_RESETTRIG_TIMA_TFCMP2 |
|
LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT |
g4, h7 |
LL_HRTIM_SYNCIN_SRC_GPIO |
|
LL_HRTIM_SYNCIN_SRC_TIM_EVENT |
g4, h7 |
LL_HRTIM_SYNCIN_SRC_TIM1_TRGO |
|
LL_HRTIM_TIMER_A |
g4, h7 |
LL_HRTIM_TIMA |
|
LL_HRTIM_TIMER_ALL |
g4, h7 |
LL_HRTIM_TIM_ALL |
|
LL_HRTIM_TIMER_B |
g4, h7 |
LL_HRTIM_TIMB |
|
LL_HRTIM_TIMER_C |
g4, h7 |
LL_HRTIM_TIMC |
|
LL_HRTIM_TIMER_D |
g4, h7 |
LL_HRTIM_TIMD |
|
LL_HRTIM_TIMER_E |
g4, h7 |
LL_HRTIM_TIME |
|
LL_HRTIM_TIMER_F |
g4 |
LL_HRTIM_TIMF |
|
LL_HRTIM_TIMER_MASTER |
g4, h7 |
LL_HRTIM_MASTER |
|
LL_HRTIM_TIMER_NONE |
g4, h7 |
LL_HRTIM_TIM_NONE |
|
LL_HRTIM_TIMER_X |
g4, h7 |
LL_HRTIM_TIMX |
|
LL_HRTIM_UPDATEGATING_DMABURST |
g4, h7 |
LL_HRTIM_UPDATEGAT_DMABURST_COMPLETE |
|
LL_HRTIM_UPDATEGATING_DMABURST_UPDATE |
g4, h7 |
LL_HRTIM_UPDATEGAT_DMABURST_UPDATE |
|
LL_HRTIM_UPDATEGATING_INDEPENDENT |
g4, h7 |
LL_HRTIM_UPDATEGAT_INDEPENDENT |
|
LL_HRTIM_UPDATEGATING_UPDEN1 |
g4, h7 |
LL_HRTIM_UPDATEGAT_TIM16_OC |
|
LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE |
g4, h7 |
LL_HRTIM_UPDATEGAT_TIM16_OC_UPDATE |
|
LL_HRTIM_UPDATEGATING_UPDEN2 |
g4, h7 |
LL_HRTIM_UPDATEGAT_TIM11_OC1 |
|
LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE |
g4, h7 |
LL_HRTIM_UPDATEGAT_TIM17_OC |
|
LL_HRTIM_UPDATEGATING_UPDEN3 |
g4, h7 |
LL_HRTIM_UPDATEGAT_TIM6_TRGO |
|
LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE |
g4, h7 |
LL_HRTIM_UPDATEGAT_TIM6_TRGO_UPDATE |
|
LL_HRTIM_UPDATETRIG_MASTER |
g4, h7 |
LL_HRTIM_UPDATETRIG_MASTER_UPDATE |
|
LL_HRTIM_UPDATETRIG_TIMER_A |
g4, h7 |
LL_HRTIM_UPDATETRIG_TIMA_UPDATE |
|
LL_HRTIM_UPDATETRIG_TIMER_B |
g4, h7 |
LL_HRTIM_UPDATETRIG_TIMB_UPDATE |
|
LL_HRTIM_UPDATETRIG_TIMER_C |
g4, h7 |
LL_HRTIM_UPDATETRIG_TIMC_UPDATE |
|
LL_HRTIM_UPDATETRIG_TIMER_D |
g4, h7 |
LL_HRTIM_UPDATETRIG_TIMD_UPDATE |
|
LL_HRTIM_UPDATETRIG_TIMER_E |
g4, h7 |
LL_HRTIM_UPDATETRIG_TIME_UPDATE |
|
LL_HRTIM_UPDATETRIG_TIMER_F |
g4 |
LL_HRTIM_UPDATETRIG_TIMF_UPDATE |
LL HRTIM macros ¶
|
HAL1 |
series |
HAL2 |
|---|---|---|
|
LL_HRTIM_ReadReg |
g4, h7 |
LL_HRTIM_READ_REG |
|
LL_HRTIM_WriteReg |
g4, h7 |
LL_HRTIM_WRITE_REG |
|
__LL_HRTIM_GET_OUTPUT_STATE |
g4, h7 |
LL_HRTIM_GET_OUTPUT_STATE |
LL HRTIM functions ¶
|
HAL1 |
series |
HAL2 |
|---|---|---|
|
LL_HRTIM_ConfigDLLCalibration |
g4 |
LL_HRTIM_SetDLLCalibrationRate |
|
LL_HRTIM_DeInit |
g4, h7 |
Removed / sequence changed |
|
LL_HRTIM_IsDisabledOutput |
g4, h7 |
LL_HRTIM_IsEnabledOutput |
|
LL_HRTIM_ResumeUpdate |
g4, h7 |
LL_HRTIM_EnableUpdate |
|
LL_HRTIM_SuspendUpdate |
g4, h7 |
LL_HRTIM_DisableUpdate |
|
LL_HRTIM_TIM_SetCaptureTrig |
h7 |
LL_HRTIM_TIM_SetCaptureTrig |